The present trend in the electronics industry is toward increasing the functionality of circuit boards by packing an ever-increasing number of surface-mounted components on the board. The increasing functionality of each board, resulting from the dense packing of surface-mounted components, has made testing of the board by conventional techniques ever more difficult. For this reason, the Institute of Electronic and Electrical Engineers (IEEE) is presently considering a standard (P 1149.1) for testing circuit boards by a technique known as boundary scan. The IEEE P1149.1 proposal is substantially identical to the boundary scan architecture adopted by the Joint Test Action Group (JTAG) of Europe and North America which is described in the document JTAG Boundary Scan Architecture Version 2.0, published in March, 1988, herein incorporated by reference.
In accordance with the JTAG and IEEE boundary scan architecture proposals, individual boundary scan cells in a device (i.e., an integrated circuit) are serially linked to establish a boundary scan register. Under the control of a test access port (TAP) controller in each device, each bit of an externally generated test vector TDI is shifted into a successive one of the cells. Thereafter, the bit in each "output" cell (i.e., a cell whose output is fed to another cell) is applied to each "input" cell (i.e., a cell whose input is coupled to an output cell). The bit at the input of each input cell is captured (i.e., retained in place of the bit originally shifted into the cell). After the bits are captured, the bits are shifted out of all of the cells and are compared to the bits in a vector expected to be produced when no faults are present. Any deviation indicates a faulty connection between cells.
The TAP controller in each device is a sixteen-state, finite state machine which is controlled by a test mode select (TMS) control signal applied to the controller. By applying a TMS signal having a particular bit pattern, the TAP controller can be shifted through its sixteen states to initiate the application and capture of the bits of the test vector TDI as well as other operations. A large majority of the sixteen states of the TAP controller are entered into and remain active during an interval of fixed duration corresponding to the period between successive pulses (clock cycles) of a periodic clock signal. However, several of the sixteen states of the TAP controller remain active during several clock cycles. For example, when test data movement takes place, the TAP controller remains in a shift state for several clock cycles. Similarly, the TAP controller can remain in a pause state for several clock cycles.
At the present time, there are two proposed methods for generating the particular bit sequences of the TMS signal needed to step or shift the TAP controller through its sixteen states. The first approach is to provide a random access memory (RAM) for storing the required bit sequences. This approach affords great flexibility since any arbitrary sequence of bits can be output by appropriately addressing the corresponding RAM location in which the segment is stored. The disadvantage of this approach is that the RAM required to store the bit sequences adds to the overall boundary scan circuitry cost. Another approach to generating the TMS signal bit sequences is to provide a finite state machine. Such a finite state machine may require less circuitry but offers less flexibility. With a finite state machine, only a limited number of predetermined bit sequences can be generated.
Thus, there is a need for a technique for generating control signal bit sequences which affords high flexibility, yet can be practiced without the requirement of extensive circuitry.